1. Technical Field
The present invention relates in general to an improved data processing system, and in particular to a method and system for temporarily buffering condition register data within the data processing system. Still more particularly, the present invention relates to a method and system for temporarily buffering condition register data in a condition register renaming table having a plurality of condition register rename buffers for facilitating out-of-order and speculative instruction execution within a data processing system.
2. Description of the Related Art
As the quest for greater data processing system performance continues, central processing unit (CPU) designers have implemented superscalar data processing systems that are capable of issuing multiple independent instructions into multiple execution pipelines, wherein multiple instructions are executed in parallel. An example of such a superscalar data processing system is the superscalar microprocessor sold under the trademark "PowerPC" by IBM Microelectronics and Motorola Semiconductor. The "PowerPC" architecture is described in more detail in various user's manuals, including "PowerPC 603-RISC MICROPROCESSOR USER'S MANUAL," copyright 1994, IBM Part No. MPR603UMU-01.
Within the superscalar microprocessor, instructions are fetched from an instruction cache and dispatched in program order to one of a plurality of execution units, wherein the instruction is executed by an execution unit appropriate for the particular type of instruction. For example, floating-point instructions are dispatched to one or more floating-point execution units, while fixed-point instructions are dispatched to one or more integer units. While instructions are dispatched in program order, instruction execution may occur out of order, depending upon availability of execution units and other data processing system resources.
In the superscalar processor, instructions may be dispatched, executed, and "finished" before other instructions that were previously dispatched. In order to prevent out-of-order instruction execution from placing data in an architected register at the wrong time, instruction execution is "completed" in program order by a completion unit. Thus, a subsequently dispatched instruction may "finish" before a previously dispatched instruction finishes, but the subsequently dispatched instruction may not be "completed" before completion of the previously dispatched instruction.
As is known in the art, "PowerPC" includes a condition register (CR) that includes bit fields that are set or reset to reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical operations, and provides a mechanism for testing and branching. A problem occurs, however, when a condition register data dependent instruction (i.e., an instruction that is dependent upon current data being in the condition register) is executed following out-of-order execution of prior instructions that modify data in the condition register.
In the prior art, dispatch of a condition register modifying instruction may be delayed because too many instructions that modify this same condition register cannot be dispatched in the same cycle.
In addition to the problem of dispatching too many condition register modifying instructions in one cycle, branch instructions that depend on data in the condition register (e.g., conditional branch instructions) may be delayed due to the delay in dispatching condition register modifying instructions. If the resolution of such conditional branch instructions is delayed, processing may be further delayed because of the time required to fetch instructions in the new path from instruction memory once the conditional branch instructions is resolved.
In addition to out-of-order execution, superscalar data processing systems may speculatively execute instructions following a conditional branch, if such conditional branch has not been resolved. Such speculative execution causes problems when a conditional branch is speculatively resolved to execute instructions in what is later determined to be the wrong instruction path. When such missprediction of a conditional branch occurs, registers must be restored to the state that existed before misspredicting the condition branch. For example, the condition code register must be restored to the state that existed before executing condition register modifying instructions in the misspredicted branch.
In view of the discussion above, it should be apparent to those persons of ordinary skill in the art that a need exists for a method and system that permits dispatching of multiple condition register modifying instructions in the same cycle, early resolution of condition register data dependent instructions, and efficient cancellation of condition register data resulting from erroneous speculative execution of condition register modifying instructions.